1. Field of the Invention
The present invention relates to an improvement of a writing method in a DRAM (dynamic random access memory).
2. Description of the Prior Art
FIG. 1 is a block diagram showing an example of a whole construction of a DRAM. This DRAM comprises a memory cell array 1, a column decoder 2, a row decoder 3, a data register 4 and a selector 5. The memory cell array 1 comprises a plurality of memory cells arranged in a matrix including columns and rows, those memory cells being located at respective intersections of a plurality of bit lines connected to the column decoder 2 and a plurality of word lines connected to the row decoder 3.
Referring to a circuit diagram of FIG. 2, one column of memory cells is illustrated. The memory cell array 1 further comprises a sense amplifier 6. Bit lines BL and BL are connected to data lines Data and Data through FETs (field effect transistors) and inverted data appears on the data line Data. A sense signal Sn changes between a level Vcc/2 and a ground level, and another sense signal Sp changes between the level Vcc/2 and a level Vcc. Each of the memory cells 7 comprises an FET and a capacitor, the FET having its drain connected to the bit line BL or BL and its gate connected to a word line WL. The capacitor has one electrode connected to a cell plate potential Vcp and the other electrode connected to the source of the FET. A pair of bit lines BL and BL are set to an equal bit line voltage V.sub.BL by means of an equalization signal EQ.
A data transfer control signal DT controls transfer of data between the data register 4 and the bit lines BL and BL. The data register 4 is connected to serial input/output lines SIO and SIO through FETs. Inverted data appears on the serial input/output line SIO.
Referring to a circuit diagram of FIG. 3, an example of the column decoder 2 is illustrated. A desired pair of bit lines BL and BL is selected by a column selection signal YSelect corresponding to a column address CAi. A reference character FW represents a data control signal at the time of flash write.
Referring to FIG. 4, an example of the row decoder 3 is illustrated. The selector 5 in FIG. 1 comprises a circuit similar to that of the column decoder shown in FIG. 3.
A conventional data writing method in the DRAM thus constructed will be described in the following.
FIG. 5A is a timing chart showing a conventional data writing method in the case of data transfer. In transferring data, an address Ads is read at a fall of a row address strobe input signal RAS.
When the row address strobe input signal RAS falls, the data transfer control signal DT rises and data of the data register 4 appears on the bit line BL. Then, the potential of the word line WL rises and memory cells of the i row are activated. A signal S for activating the sense amplifier 6 rises and the sense amplifier 6 is operated to determine a high level or a low level of the data appearing on the bit line BL. When the row address strobe input signal RAS rises, the data transfer control signal DT falls and the potential of the word line WL also falls. Thus, the high or low data of the data register 4 appearing on the bit line BL is written into the memory cells 7 of the i row. When the potential of the word line WL falls, the equalization signal EQ rises to cause the potentials of the bit lines BL and BL to be Vcc/2.
The same procedures as described above are executed to write the same data as that of the i row into the j row.
FIG. 5B is a timing chart showing a conventional data writing method in the case of flash write.
In the case of flash write, an address Ads is read at a fall of the row address strobe input signal RAS. When the row address strobe input signal RAS falls, the data control signal FW becomes low, causing the signals YSelect for selecting the bit lines to be all high. As a result, data of the data line Data appears on all the bit lines BL. Assuming that the data is high, the high data appears on all the bit lines BL. After that, the potential of the word line WL of the i row of the address Ads rises to activate the memory cells 7 of the i row. The signal S for activating the sense amplifier 6 rises to determine the high data on the bit lines BL. When the row address strobe input signal RAS rises, the data control signal FW becomes high in response thereto and the signal YSelect for selecting the bit lines becomes low. When the word line WL of the i row becomes low, the equalization signal EQ rises to cause the potentials of the bit lines BL and BL to be Vcc/2.
Thus, the high data is written in the memory cells 7 of the i row. The same data as that of the i row can be written into the j row by executing the same procedures as described above. When data is low, it can be written in a similar manner as in the case of the high data.
It is indicated in FIGS. 5A and 5B that a power supply current Icc of about 100 mA flows at each rise of the signal S for activating the sense amplifier 6.
According to the conventional writing methods, the sense amplifier 6 is activated each time the address Ads is changed, and the large power supply current Icc flows each time. In addition, since one cycle period is almost equal to a normal read/write cycle, it takes much time to write data into a large number of addresses.